1. Field of the Invention
The present invention relates to method for a manufacturing a substrate for a semiconductor device and more particularly, gettering impurities in the substrate.
2. Description of the Prior Art
Generally, a semiconductor device is formed on a thin substrate referred to as a wafer. Often, the wafer contains impurities, such as, Fe, etc., therein. Once a semiconductor device is formed in a device formation region of the wafer which contains impurities, the formed semiconductor device operates erroneously.
To remove the impurities from the device formation region of the wafer, a layer is formed on the bottom surface of the wafer and distortions are caused between the wafer and the layer. As a result, the impurities are trapped in the distortions which are formed on the bottom surface of the wafer. Then, the semiconductor device is formed on the top surface of the wafer. This technique is referred to as "gettering" to those skilled in the art. When the gettering function is provided from outside of the wafer, it is referred to as EG(Extrinsic Gettering).
The mechanism of EG will be described below. FIG. 1A and FIG. 1B illustrate particles 10 of the polysilicon layer formed on the bottom surface of the wafer. For easy reference, FIG. 1A and FIG. 1B are shown upside down, meaning the bottom surface of the wafer is shown in the up side of the figures and the top surface of the wafer is shown in the down side of the figures. When growing a polysilicon layer on the wafer, the particles 10 of the polysilicon layer are grown as illustrated in FIG. 1B. At the same time, distortion ST1 occurs at a surface S1 of the wafer 1 where the wafer faces particles 10 of the polysilicon layer. Also, a distortion ST2 occurs at a surface S1 of the wafer 1 where the particles 10 of the polysilicon layer overlap each other. Contained impurities such as Fe, etc. of the wafer 1 are trapped in the distortions. That is, on carrying out heat treatment to the wafer 1 on which a polysilicon layer is formed, the contained impurities in the wafer 1 are effectively trapped in the distortions.
Next, conventional gettering is described. A poly silicon layer 20 is formed on top and bottom surfaces of wafer 1 as illustrated in FIG. 2A, utilizing the CVD(Chemical Vapor Deposition) method (see FIG. 2B), replace removing the polysilicon layer 20 on the top surface of the wafer 1 (up side of FIG. 2) by chemical etching the polysilicon layer 20 exists on the bottom side of the wafer l (see FIG. 2C). Then, the distortions occur between the polysilicon layer 20 and the wafer l (see FIG. 1B).
Incidentally, the wafer 1 has relative stress against the polysilicon layer 20 to inside (as shown in by arrow 200 of FIG. 3A and FIG. 3B), while the polysilicon layer 20 formed on the bottom surface of the wafer 1 has relative stress against the wafer 1 to outside (as shown in an arrow 200 of FIG. 3A and FIG. 3B). The discrepancies of these stresses between wafer l (the arrow 200) and the polysilicon layer 20 (the arrow 100), cause distortion ST10 and distortion ST20 (see FIG. 3A). Therefore, the impurities in the wafer are trapped in the distortion ST10 and distortion ST20.
When, heat treatment is carried out to the wafer 1 which is shown in FIG. 2C, the trapping of is accelerated and the impurities are trapped in the distortions more effectively. After the heat treatment, the polysilicon layer 20 is partially removed from the wafer 1.
However, wafer 1 has relative stress to the inside (the arrow 100 as shown in FIG. 3A and FIG. 3B), and the polysilicon layer 20 keeps relative stress to the out side (the arrow 200 as shown in FIG. 3A and 3B). Provided, the polysilicon layer 20 still exists after the partial removal on the bottom surface of the wafer 1 as it is shown in FIG. 2C, the wafer 1 receives stress as illustrated by an arrow 300 in FIG. 3B. This is due to discrepancies of stress direction between wafer 1 (compression stress represented by arrow 100 in FIG. 3A and FIG. 3B) and the polysilicon layer 20 (stretch stress represented by the arrow 200 in FIG. 3A and FIG. 3B). Once the wafer 1 receives the stress represented by the arrow 300, the wafer 1 curves slightly as shown in FIG. 3B. The stress represented by the arrow 300 causes curvature of the wafer 1 (see FIG. 3B). Furthermore, the heat treatment accelerates the stress represented by the arrow 300, so that the wafer 1 curves more as shown in FIG. 3C.
When the wafer 1 is curved as shown on FIG. 3C, it decreases the yield of semiconductor device production. Also the curved wafer affects the production steps of making a semiconductor device, especially the curvature affects the alignment step. The curvature of the wafer 1 causes misalignment between center the part of the wafer 1 and the edge part of the wafer 1. The misalignment to the wafer 1 decreases reliability of the semiconductor device, even when the curvature is slight. Accuracy of alignment is required, particularly for the steps of a highly integrated semiconductor device.